The development of a computer graphics system creates the need for fast memories capable of storing huge amounts of data, such as 3-D graphics data. Among such memories are cached memories developed to improve DRAM main memory performance by utilizing a faster SRAM cache memory for storing the most commonly accessed data. For example, U.S. Pat. No. 5,566,318 discloses an enhanced DRAM that integrates a SRAM cache memory with a DRAM on a single chip. Sense amplifiers and column write select registers are coupled between the SRAM cache and the DRAM memory array. A column decoder is associated with the SRAM cache for providing access to the desired column of the SRAM. A row decoder is associated with the DRAM memory array to enable access to particular rows of the DRAM. Input/output control and data latches receive data from the SRAM to provide data output via data input/output lines. The current row of data being accessed from the DRAM memory array is held in the SRAM cache memory. Should a cache "miss" be detected, the entire cache memory is refilled from the DRAM memory array over a DRAM-to-cache memory bus.
As a way of improving speed and performance of a RAM, a dual-port RAM has been developed which enables two separate input/output ports to access the memory array. However, the dual-port RAM cannot provide effective control of data input and output, because its ports are not interchangeable. For example, data traffic cannot be redistributed between the ports, when one of them is overloaded and the other is underloaded.
Accordingly, it would be desirable to provide a multi-port RAM (MPRAM) chip having interchangeable input/output data ports.
In a synchronous memory, all operations may be referenced to the rising edge of the internal clock. At high frequencies, the internal clock must be controlled very accurately because the time from a rising edge of the internal clock to the next rising edge becomes very short. Therefore, any shift or skew in the internal clock would cause the memory to operate incorrectly.
This is especially important for output of data from an MPRAM. The output data may be driven out of the MPRAM to an external controller at the rising edge of the internal clock. At high clock frequencies, any skew in the internal clock rising edge will delay the output of data to the external controller. As the controller has a set time window during which it can accept data from the memory, the delay in data output will cause the controller to miss the output data. Therefore, the external controller must reduce the clock frequency to allow the output data to be within the set data window. This reduction would limit the speed and performance of the MPRAM.
Moreover, different groups of data pins may be required to be on opposite corners of a memory chip. In this case, the internal clock driving one group of data pins will be skewed with respect to the internal clock driving the data pins located on the opposite corner. To compensate for data output shift caused by the skewed clocks operating frequency of the memory should be reduced. As a result, the performance of the memory would deteriorate.
The skew of internal clocks within an MPRAM chip depends on gate and parasitic loading of physical clock lines carrying the internal clock signals. The gate loading of a line corresponds to the number of logic elements connected to the lines. Parasitic resistance and capacitance of a line determine its parasitic loading.
Thus, it would be desirable to provide an MPRAM with a clocking scheme that allows the loading of physical clock lines to be decreased, to reduce the skew of internal clocks.